Texas Instruments XIO1100 x1 PCI Express™ PHY
Texas Instruments XIO1100 x1 PCI Express™ PHY
Texas Instruments XIO1100 x1 PCI Express™ PHY that is compliant with PCI Express Base Specification Revision 1.1. This device interfaces the PCI Express Media Access Layer (MAC) to a PCI Express serial link by using a modified version of the interface described in PHY Interface for the PCI Express. The TI-PIPE interface is a pin-configurable interface that can be configured as either a 16-bit or an 8-bit interface.
The 16-bit TI-PIPE interface is a 125MHz 16-bit parallel interface with a 16-bit output bus (RXDATA) that is clocked by the RXCLK output clock and a 16-bit input bus (TXDATA) that is clocked by the TXCLK input clock. Both buses are clocked using Single Data Rate (SDR) clocking in which the data transitions are on the rising edge of the associated clock.
The 8-bit TI-PIPE interface is a 250MHz 8-bit parallel interface with an 8-bit output bus (RXDATA) that is clocked by the RXCLK output clock and an 8-bit input bus (TXDATA) that is clocked by the TXCLK input clock. Both buses are clocked using Double Data Rate (DDR) clocking in which the data transitions are on both the rising edge and the falling edge of the clock.
The XIO1100 PHY interfaces to a 2.5Gbps PCI Express serial link with a transmit differential pair (TXP and TXN) and a receive differential pair (RXP and RXN). Incoming data at the XIO1100 PHY get a receive differential pair (RXP and RXN) that is forwarded to the MAC on the RXDATA output bus. Data received from the MAC on the TXDATA input bus is forwarded to the XIO1100 PHY transfer differential pair (TXP and TXN).
Features
X1 PCI Express™ Serial Link PCI Express 1.1 Compliant
Selectable Reference Clock (100MHz, 125MHz)
Low-Power Capability
TI-PIPE MAC Interface Source-Synchronous TX and RX Ports
125MHz TX/RX Clocks
Selectable 16-Bit SDR or 8-Bit DDR Mode
100-Pin MicroStar™ BGA Package
Selectable 1.5V or 1.8V LVCMOS Buffers
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